1. Field of the Invention
The present invention relates to microprocessor power management, and more particularly to providing means for dynamically adjusting the power consumed by a microprocessor in a manner that does not incur undue delays.
2. Description of the Related Art
Power consumption management is an important issue for several types of computing systems, including portable devices, laptop computers, and environmentally friendly computers (i.e., “green” computers). Battery life, for example, is a significant issue for most laptop computer users. The microprocessor consumes a significant amount of power, so that it is often the target of power reduction techniques. The challenge for microprocessor designers is to provide a means for changing the power state of the microprocessor in a smooth and relatively seamless fashion, and to complete such transition as quickly as possible. Several different techniques for modifying the power consumption of a microprocessor are known, including, for example, dynamically changing the frequency of the microprocessor's core clock signal. The power consumption of a microprocessor is proportional to the frequency of its core clock signal.
FIG. 1 is a simplified block diagram of a conventional power management system 100, which illustrates how frequency-based power management is accomplished in existing microprocessors. A SENSE interface 101 (e.g., sense bus or the like) provides one or more power sense signals to power management logic 103. The power management logic 103 determines a power state at which the microprocessor should be executing based on the immediate and/or previous states of the sense signals of the SENSE interface 101. Exemplary sense signals on the sense interface 101 include, for example, values of machine specific registers written by software, such as the operating system (OS) software or the like, temperature transducers (not shown), remaining power signals, etc. To execute at a particular power state, the power management logic 103 establishes value on a core ratio (CORERATIO) bus which is provided to a phase lock loop (PLL) 105. The PLL 105 generates a CORE CLOCK signal as a function of the frequency of a BUS CLOCK signal and the value of the CORERATIO bus from the power management logic 103, where the CORE CLOCK signal is fed back to the PLL 105. A core clock ratio value of three (3), for example, would direct the PLL 105 to generate the CORE CLOCK signal that is three times the frequency of the BUS CLOCK signal.
As understood by those skilled in the art, the PLL 105 generally multiplies the frequency of the external BUS CLOCK signal and generates the CORE CLOCK signal for internal use. For example, a 500 megahertz (MHz) BUS CLOCK signal is multiplied by eight (e.g., CORERATIO=8) to yield a 4.0 gigahertz (GHz) machine during full power conditions. The PLL 105 keeps the CORE CLOCK signal in phase with the BUS CLOCK signal. The CORERATIO bus value indicates a reduced frequency of operation for reduced power levels, such as a 25% power level (CORERATIO=2), a 50% level (CORERATIO=4), a 75% level (CORERATIO=6), etc.
The conventional power management system 100, which provides for dynamically changing the power state of a microprocessor, is disadvantageous because the PLL 105 incurs a significant delay to change from one frequency to the next. The delay is often substantial, such as on the order of hundreds of clock cycles. The computer system may be temporarily suspended during each PLL frequency change delay. For example, if an application is running on the microprocessor that is performing a relatively simple function, such as a DVD decode or the like, it is very likely that power can be conserved by running at a reduced frequency, such as half-frequency. The power management logic 103 detects power sense signals indicating a reduced power state and directs the PLL 105 via the CORERATIO bus to ramp down in frequency. A commensurate delay occurs while the PLL 105 is ramping down. In addition, other tasks may be invoked by the OS during or shortly after that time, which require immediate changeover back to full operating frequency. Such events cause additional delays and performance degradation until the PLL 105 ramps back up to the full operating frequency. These frequency change delays are often detected by the user, in that applications may appear to be locked up from time to time. Existing frequency modulation techniques, therefore, disadvantageously affect overall performance.